There is a current trend in computer architecture to faster and faster microprocessors. Increasing the rate of operation of microprocessors increases the computation capacity of the computer system which also requires a consequent increase in the rate of data transfer into and out of the microprocessor. Otherwise, the microprocessor will stall waiting for external data transfers, such as into and out of the main computer system memory or external cache memory. Thus, the computational capacity of the computer would be limited not by the rate of operation of the microprocessor but by the data transfer rate with external memories.
There are several approaches to increasing the data transfer rate between the microprocessor and the memory system. First, the number of lines between the microprocessor and the memory system may be increased. It is now typical to provide 32 bit data and address busses. More advanced systems may provide data and address busses of 64 bits or 128 bits. Second, the rate of data transfer on each line between the microprocessor and the memory system may be increased.
Each of these techniques carries consequent disadvantages. Increasing the number of lines between the microprocessor and the memory system requires that the integrated circuits embodying these parts include more pins. Integrated circuit packages with large number of pins are more expensive. In addition, current high capacity microprocessors typically support plural separate busses. The first is the system bus. This is typically connected to a memory controller that interfaces with the memory system and parts of the computer system peripheral to the microprocessor. These peripheral parts include input devices, storage devices and the like. Another is a private cache bus connected to fast static random access memory (SRAM) used as instruction and data cache. Additionally, current high capacity microprocessors may also include additional private busses connected to other parts of the computer system such as graphics. With such a large number of busses already connected to the microprocessor, increasing the bus width of one or more of these busses could add greatly to the number of pin needed in the integrated circuit package. As an example, the Pentium Pro microprocessor package includes 387 pins. Of these 387 pins, 64 pins are dedicated to communication with a level two memory cache and 64 pins are dedicated to the external system bus. Conversion of these signals to differential signals on the same integrated circuit would require the package to include over 500 pins. Such an integrated circuit package would be very expensive.
Increasing the speed of data transfer of each bus line has other disadvantages. Integrated circuits embodying the microprocessor and the memories are generally constructed of complementary metal oxide semiconductor (CMOS). These type circuits generally require more power when operating at higher speeds. In portable devices, minimal electrical power consumption is very desirable. Even in line powered applications, excess power requirements are a problem. Electrical power consumption causes heat within the integrated circuit. High heat generation due to electrical power consumption may require aggressive heat management techniques. These include more expensive packaging and fans to greater airflow. These problems with heat generation are greater for externally connected lines than for lines included within the integrated circuit. Lines within the integrated circuit are generally shorter and smaller than externally connected lines. Thus, these lines have a lower capacitance than externally connected lines. Consequently, the line drivers for externally connected lines must switch more charge than those for internal lines. This requires larger MOS devices in the external drivers to switch the larger required currents. Thus, power consumption and heat dissipation become problems.
One method to reduce the amount of charge switched is to reduce the voltages used. In the foreseeable future, high speed busses may use voltage limits as low as 1 volt. This low voltage is close to the voltage threshold of MOS devices, that is the minimum required gate voltage to switch the channel to conduct. Thus further significant reductions in the voltages used is not expected due to reduced noise margins in the signal lines. Switching from single lines to differentially driven lines would enable greater speeds of data transfer by enhancing the noise margin. However, providing differential drivers and receivers on the integrated circuits would greatly increase the number of pins required. This would increase the cost of the integrated circuit package. Accordingly, none of these proposed solutions has been widely adopted.